Audio configuration

Audio Agent has 2 types of audio interfaces, analog and digital(I2S/PCM/SPDIF). Both are configurable with the AUDIO_ANALOG and AUDIO_DIGITAL parameters. The AUDIO parameter allows the selection of the audio input and output separately for the A2DP and HFP profiles.

Analog interface

The analog configuration is stored in the parameter AUDIO_ANALOG:

AUDIO_ANALOG = (input_gain) (output_gain) (micbias) (preamp)

  • input_gain: Codec input gain (0-22).

  • output_gain: Codec output gain (0-15).

  • micbias: Configures mic bias (2.6 V). 0: Disable the microphone bias, 1: Turn the microphone bias on only when there is audio, 2: Enable the microphone bias all the time.

  • preamp: ON to enables the microphone pre-amp. This results in an additional 20dB of input gain on that channel. In designs that use a microphone, enabling this functionality is recommended.

Note that thoses parameters are taken into account when connecting the audio. For HFP/A2DP, the output gain is adjusted by the DSP based on the current volume. In that case the value is not relevant and the VOLUME command shall be used instead. When cVc is active, the input gain is also set by the DSP. The cVc configuration can be changed using CVC_CFG command.

Digital interface

The digital configuration of the digital audio interface is stored in the parameter AUDIO_DIGITAL:

AUDIO_DIGITAL = (format) (rate) (param1) (param2)

  • format:

    0 - I2S 1 - PCM 2 - SPDIF

  • rate: Word clock (WCLK) in hertz for I2S/ PCM or output rate for SPDIF. Please note that I2S/PCM support re-sampling for HFP and A2DP, the supported rates are detailed in the Resampling section.

  • param1: Bit clock scaling factor for I2S. Master clock in kHz for PCM. Not used for SPDIFF.

  • param2: refer to the tables below. Depends on the format.

By default, I2S is selected and configured in Master mode, Left Justified with 1 Bit delay, 16 bps with a Word clock (WCLK) at 44100Hz and a Bit clock (BCLK) at 2.822Mhz (64*44100Hz)

Please note:

In Slave mode, due to hardware limitations, a Bit clock (BCLK) of at least 4*bps*WCLK and up to 256*WCLK must be supplied.

In Master mode we also recommend to generate a Bit clock of at least 4*bps*WCLK. The Bit clock scaling factor should be superior or equal to 4*bps. The following tables describe param2 of the digital interface for each format:

I2S

[24:31]

Not used.

[16:23]

Bits per sample (bps). If larger than the internal format used by Audio Agent, the additional bits will be output as zeros in the least significant bits.

[12:15]

Audio attenuation in 6 dB steps. Valid range: 0 to 15 inclusive.

[11]

Master mode - clock and sync will be generated by the I2S hardware.

[10]

Justify format - 0: left justified, 1: right justified.

[9]

Left justify delay - 0: left justified formats: 0 is MSB of SD data occurs in the first SCLK period following WS transition. 1: MSB of SD data occurs in the second SCLK period.

[8]

Channel polarity Valid values: 0 (SD data is left channel when WS is high), 1 (SD data is right channel when WS is high).

[7]

Audio attenuation enable - 0: 17 bit SD data is rounded down to 16 bits. 1: the audio attenuation defined in Audio attenuation is applied over 24 and 20 bits of incoming data with saturated rounding. Requires crop enable to be 0.

[5:6]

Not used.

[3:4]

Justify resolution - Resolution of data on SD_IN, 00=16 bit, 01=20 bit, 10=24 bit, 11=Reserved. This is required for right justified format and with left justified LSB first.

[2]

Crop enable 0: 17 bit SD_IN data is rounded down to 16 bits. 1: only the most significant 16 bits of data are received.

[1]

Start Tx sampling 0: during low wclk phase. 1: during high wclk phase.

[0]

Start Rx sampling 0: during low wclk phase. 1: during high wclk phase.

PCM

[26:31]

Not used.

[25]

Enable PCM master mode - clock and sync will be generated by the PCM hardware.

[22:24]

PCM slot count - Valid range 0 to 4 inclusive. If 0, slot count will be derived from master clock and synchronisation rate.

[21]

Enable PCM Manchester encoding mode.

[20]

Enable PCM short synchronisation - Short frame sync (falling edge indicates start of frame), rising edge indicates start of fame in long sync mode.

[19]

Enable PCM Manchester slave mode - Force transmit frames to follow receive frames with constant delay. Requires extended features to be enabled.

[18]

Enable PCM sign extend - Sign extend 13/8 bit sequence to 16 bit sequence, else pad with the STREAM_PCM_AUDIO_GAIN for 13-bits or 0s for 8 bits.

[17]

Enable PCM LSB first - Transmit data LSB first.

[16]

Enable PCM Tx tristate - 0: drive PCM_OUT continuously. 1: tri-state PCM_OUT immediately after falling edge of PCM_CLK in the last bit of an active slot, assuming the next slot is not active.

[15]

Enable PCM Tx tristate rising edge - 0: tri-state PCM_OUT immediately after falling edge of PCM_CLK in last bit of an active slot, assuming the next slot is also not active. 1: tri-state PCM_OUT after rising edge of PCM_CLK.

[14]

Enable PCM synchronisation suppress - Suppress PCM_SYNC while generating PCM_CLK (in master mode). Some CODECs (connected to the PCM interface) use this to enter a low power state.

[13]

Enable PCM GCI mode.

[12]

Mute PCM_DATA output.

[11]

Enable PCM long length sync - Set PCM_SYNC to 8 or 16 PCM_CLK cycles.

[10]

Enable PCM sample rising edge - Sample PCM_DATA on rising edge of PCM_CLK

[7:9]

Rx rate delay - Selects the number of clocks to wait before receive DDS update rate is changed to match the new internal clock frequency. Valid range: 0 to 7 inclusive.

[5:6]

Sample format - Valid values: 0 (13 bits in 16 cycle slot duration), 1 (16 bits in 16 cycle slot duration), 2 (8 bits in 16 cycle slot duration), 3 (8 bits in 8 cycle slot duration).

[3:4]

Manchester receive offset - When in Manchester mode, selects the delay between receiving the start bit and sampling the first significant bit from the voice sample. Valid range: 0 to 3 inclusive

[0:2]

Audio gain - Valid range: 0 to 7. Used to pad the end 3 bits of a 13 bit PCM sample. It is used by some CODECs (connected to the PCM interface) to allow their gain to be controlled.

SPDIF

[4:31]

Not used.

[3]

Set the reporting mode for the SPDIF Rx channel Status.

[2]

Set the SPDIF Tx channel B status same as that of channel A.

[1]

Set the SPDIF Tx channel status word value.

[0]

Set SPDIF RX in auto rate detect mode.

Resampling

Re-sampling is supported for the digital audio input and output. Here are the list of supported rates per profiles:

  • HFP-AGHFP:

    8000, 16000, 32000, 44100, 48000, 96000

  • A2DP:

    44100, 48000